16-bit SRAM


This code in block 1360 is loaded into node 008 of the host chip. It provides access to SRAM, aided by nodes 007 (left) which has 18 data pins and 009 (right) which has 18 address pins. 008 has 4 control pins.

There are entry points for random and sequential read/write and read/modify/write. The challenge is to optimize sequential read, since reading is more common than writing. The 3 nodes cooperate to do so. For sequential

Paging

The CY62167EV18 SRAM chip has 20 address pins to access 1 MW of 16-bit wide memory. The GA144 has 18 address pins accessing a page of 262,144 words and 2 others that select 1 of 4 pages.

The first 4 words of 008 RAM specify select bits for the 4 pages

Register b normally holds left. Temporarily right or io.

!pg

pg

page

we+

inc

ad

Passes an address to 009

read

Entry point for random read

rd

Does the work of reading

+read

Sequential read entry point

write

Entry point for random write

wr

Does the work of writing

we

+write

Sequential write entry point

rw

Random read/write entry point

-rw

Does the work of read/write

+rw

Sequential read/write entry point

init